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Showing content with the highest reputation on 04/04/2020 in all areas

  1. 1 point
    Hello everyone! I'm new to this forum, and let me say that I love to see the love and conversation about MiniDisc keep going on I'm popping in just to let you know that I've recently released an app for NetMD devices. I wrote the app mainly for myself, but I thought it might be useful for some of you too! So, and here's the link to use it -> https://stefano.brilli.me/webminidisc/ And here's a short demo of how app works Any feedback is welcome! Stefano
  2. 1 point
    I'm wayyy off topic here, but if you like my waffle... These days (since early 1990s) we do the logic design with specialised software languages like SystemVerilog or VHDL, generally known as Hardware Description Languages or HDLs. This description can't be "anything and everything" you like in these languages, you have to use particular constructs in particular contexts to "infer" meaningful structures like combinational logic or flip-flops (an abstraction we call Register Transfer Level, or RTL). Then we use a process called logic synthesis which converts the HDL description into a logic netlist (AND, OR, NAND, NOR gates, flip-flops etc). This logical netlist then has to be "layed out" onto silicon by taking the transistors of each gate and mapping them onto silicon and defining the layers that are needed in the silicon (wells, channels, contacts), then these transistors have to be wired together by creating metal interconnects that join silicon contact to silicon contact in the required circuit topology. We also have to add power meshes and clock distribution networks and fix the timing of the circuit (setup and hold). Once the physical design is complete and the layout meets all of the logical and physical design rules, the design can be sent to the silicon foundry at a point we call "tape out". The foundry do the magic chemistry steps to actually fabricate our design onto a silicon wafer. Then there is test and packaging assembly and a whole load of qualification testing to be done before the device can be released as a production part. This is a design cycle that is typically between 1 and 3 years depending on the complexity and size of the design. That's an extremely brief and simplified overview, but I'm sure you could google for more detail! Back to FSMs we wouldn't usually (ever?) use a ROM style implementation on a custom chip, we'd use an HDL to infer "random logic" to build the next-state logic. The ROM method used in the project you are looking at is a clever way to implement "random logic" in one off-the-shelf chip - couple it with a bank of flip-flops (like IC9) and you have yourself the building blocks for your FSM. The clever bit now is to work out the ROM contents which is how you define the logic of your FSM and hence its function/behaviour. There are a couple of flavours of FSM, Moore and Mealy. These terms describe how the state and outputs are a function of the inputs (Moore -> outputs are only a function of the current state, Mealy -> outputs are a function of the current state and the current inputs). Your copy-bit killer is probably a Mealy machine (the output SPDIF flop stage is not part of your FSM state because it doesn't feed back into the EPROM). Anyway that's enough from me for one night!
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