kgallen Posted May 22, 2020 Report Share Posted May 22, 2020 Don't necessarily agree. That chip supports a directly connected crystal across the XIN/XOUT pins. The crystal is excited by a lower amplitude sine wave than the usual digital levels. In this application they haven't used a directly-connected crystal, they are sourcing the clock from elsewhere. The clock they have sourced is probably a full-swing digital signal, and they don't want this for XIN so they've ac coupled it with capacitor C899. -> I suspect this is as intended. Hmmm. There are a few different datasheets about but none of them are particularly comprehensive. From the CLKSEL and FS[1:0] settings looks like the input clock should be 11.2896MHz and the output 90.3168MHz. It's not stated but it would seem reasonable that the CLKA output swings to the rails of the chip supply, which is stated as 3.3V typical. However there are some voltages annotated around that chip and it doesn't look like 3.3V on CLKA, more like 1.5V. Can you clarify on your document? OK just found the SM, it says 1.7V at IC803 pin5, even though the chip supply is 3.3V. From your top oscilloscope trace, it looks ok-ish to me (at 1V/div) - it's maybe 1.5V pk-pk on your scope but you are approaching the limits of that scope - 90.3168MHz on a 100MHz BW scope. Also the probe cap is probably 20pF on top of the input pin cap and that chip has a CLOAD(max) of 15pF. Also I note the input the clock is driving, IC201 pin 20 OSCO. This chip also seems to support an external crystal on pins 19 and 20. It's likely it's ok with a low-swing clock signal on pin 20 as there will likely be a Schmitt-trigger stage internally to square-up and level shift the crystal resonance to the correct digital levels of 3.3V. -> I would still conclude IC803 is ok. But I do concede the SM seems a bit inconsistent between the schematic, the waveform page and possibly the chip datasheet. Quote Link to comment Share on other sites More sharing options...
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